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M27V401 4 mbit (512kb x 8) low voltage uv eprom and otp eprom may 1998 1/15 ai00695b 19 a0-a18 q0-q7 v pp v cc M27V401 g v ss 8 e figure 1. logic diagram low voltage read operation: 3v to 3.6v fast access time: 120ns low power consumption: active current 15ma at 5mhz standby current 20 m a programming voltage: 12.75v 0.25v programming time: 100 m s/byte (typical) electronic signature manufacturer code: 20h device code: 41h description the M27V401 is a low voltage 4 mbit eprom offered in the two range uv (ultra violet erase) and otp (one time programmable). it is ideally suited for microprocessor systems requiring large data or program storage and is organised as 524,288 by 8 bits. the M27V401 operates in the read mode with a supply voltage as low as 3v. the decrease in operating power allows either a reduction of the size of the battery or an increase in the time be- tween battery recharges. the fdip32w (window ceramic frit-seal package) hasa transparentlid which allow the user toexpose the chip to ultraviolet light to erase the bit pattern. a new pattern can then be written to the device by following the programming procedure. a0-a18 address inputs q0-q7 data outputs e chip enable g output enable v pp program supply v cc supply voltage v ss ground table 1. signal names plcc32 (k) 1 32 fdip32w (f) tsop32 (n) 8 x 20mm 32 1 pdip32 (b)
for applications where the content is programmed only one time and erasure is not required, the m27v201 is offered in pdip32, plcc32 and tsop32 (8 x 20 mm) packages. device operation the operating modes of the M27V401 are listed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl levels except for v pp and 12v on a9 for electronic signature. read mode the M27V401 has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (e) is the power control and should be used for device selection. output enable (g) is the output control and should be used to gate data to the output pins, inde- pendent of device selection. assuming that the addresses are stable, the address access time (t avqv ) is equalto the delay from e to output (t elqv ). data is availableat the output after a delay of t glqv from the falling edge of g, assuming that e has been low and the addresses have been stable for at least t avqv -t glqv . a1 a0 q0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 q7 a14 a11 g e q5 q1 q2 q3 v ss q4 q6 a17 a18 a16 a12 v pp v cc a15 ai01861 M27V401 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections description (cont'd) a1 a0 q0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 q7 a14 a11 g e q5 q1 q2 q3 q4 q6 a17 a18 a16 a12 v pp v cc a15 ai01156b M27V401 (normal) 8 1 9 16 17 24 25 32 v ss figure 2c. tsop pin connections ai00696 a17 a8 a10 q5 17 a1 a0 q0 q1 q2 q3 q4 a7 a4 a3 a2 a6 a5 9 a18 a9 1 a16 a11 a13 a12 q7 32 v pp v cc M27V401 a15 a14 q6 g e 25 v ss figure 2b. lcc pin connections 2/15 M27V401
standby mode the M27V401 has a standby mode which reduces the supply current from 15ma to 20 m a with low voltage operation v cc 3.6v, see read mode dc symbol parameter value unit t a ambient operating temperature (3) 40 to 125 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltages (except a9) 2 to 7 v v cc supply voltage 2 to 7 v v a9 (2) a9 voltage 2 to 13.5 v v pp program supply voltage 2 to 14 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum dc voltage on input or output is 0.5v with possible undershoot to 2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5v with possible overshoot to v cc +2v for a period less than 20ns. 3. depends on range. table 2. absolute maximum ratings (1) mode e g a9 v pp q0 - q7 read v il v il xv cc or v ss data out output disable v il v ih xv cc or v ss hi-z program v il pulse v ih xv pp data in verify v ih v il xv pp data out program inhibit v ih v ih xv pp hi-z standby v ih xxv cc or v ss hi-z electronic signature v il v il v id v cc codes note :x=v ih or v il ,v id = 12v 0.5v table 3. operating modes identifier a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturer's code v il 00100000 20h device code v ih 01000001 41h table 4. electronic signature characteristics table for details. the M27V401 is placed in the standby mode by applying a cmos high signal to the e input. when in the standby mode, the outputs are in a high impedance state, independent of the g input. 3/15 M27V401
symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 6. capacitance (1) (t a =25 c, f = 1 mhz ) ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 3. ac testing input output waveform ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test figure 4. ac testing load circuit high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v table 5. ac measurement conditions two line output control becauseeproms are usually used in larger mem- ory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. the two line control function allows : a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficientuse of thesetwo control lines, e should be decoded and used as the primary device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselected mem- ory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 4/15 M27V401
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v out v cc 10 m a i cc supply current e=v il ,g=v il ,i out = 0ma, f = 5mhz, v cc 3.6v 15 ma i cc1 supply current (standby) ttl e=v ih 1ma i cc2 supply current (standby) cmos e>v cc 0.2v, v cc 3.6v 20 m a i pp program current v pp =v cc 10 m a v il input low voltage 0.3 0.8 v v ih (2) input high voltage 2 v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = 400 m a 2.4 v output high voltage cmos i oh = 100 m av cc 0.7v v notes: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v table 7. read mode dc characteristics (1) (t a = 0 to 70 c or 40 to 85 c; v cc = 3.3v 10%; v pp =v cc ) symbol alt parameter test condition M27V401 unit -120 -150 min max min max t avqv t acc address valid to output valid e = v il ,g=v il 120 150 ns t elqv t ce chip enable low to output valid g = v il 120 150 ns t glqv t oe output enable low to output valid e = v il 60 80 ns t ehqz (2) t df chip enable high to output hi-z g = v il 0 50 0 50 ns t ghqz (2) t df output enable high to output hi-z e = v il 0 50 0 50 ns t axqx t oh address transition to output transition e=v il ,g=v il 00ns notes: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp. 2. sampled only, not 100% tested. table 8a. read mode ac characteristics (1) (t a = 0 to 70 c or 40 to 85 c; v cc = 3.3v 10%; v pp =v cc ) 5/15 M27V401
ai00724b taxqx tehqz a0-a18 e g q0-q7 tavqv tghqz tglqv telqv valid hi-z valid figure 5. read mode ac waveforms symbol alt parameter test condition M27V401 unit -180 -200 min max min max t avqv t acc address valid to output valid e = v il ,g=v il 180 200 ns t elqv t ce chip enable low to output valid g = v il 180 200 ns t glqv t oe output enable low to output valid e = v il 90 100 ns t ehqz (2) t df chip enable high to output hi-z g = v il 0 50 0 70 ns t ghqz (2) t df output enable high to output hi-z e = v il 0 50 0 70 ns t axqx t oh address transition to output transition e=v il ,g=v il 00ns notes: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp. 2. sampled only, not 100% tested. table 8b. read mode ac characteristics (1) (t a = 0 to 70 c or 40 to 85 c; v cc = 3.3v 10%; v pp =v cc ) system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the devices. the supply current, i cc , has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of e. the magnitude of the transient current peaks is dependent on the capacitiveand inductiveloading of the deviceat the output. the associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling ca- pacitors. it is recommended that a 0.1 m f ceramic capacitor be used on every device between v cc and v ss . this should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. in addition, a 4.7 m f bulk electrolytic capacitor should be used between v cc and v ss for every eight devices. the bulk capacitor should be located near the power supply connection point. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of pcb traces. 6/15 M27V401
symbol parameter test condition min max unit i li input leakage current v il v in v ih 10 m a i cc supply current 50 ma i pp program current e = v il 50 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = 400 m a 2.4 v v id a9 voltage 11.5 12.5 v note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 9. programming mode dc characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) symbol alt parameter test condition min max unit t avpl t as address valid to program low 2 m s t qvpl t ds input valid to program low 2 m s t vphpl t vps v pp high to program low 2 m s t vchpl t vcs v cc high to program low 2 m s t elpl t ces chip enable low to program low 2 m s t plph t pw program pulse width 95 105 m s t phqx t dh program high to input transition 2 m s t qxgl t oes input transition to output enable low 2 m s t glqv t oe output enable low to output valid 100 ns t ghqz (2) t dfp output enable high to output hi-z 0 130 ns t ghax t ah output enable high to address transition 0 ns notes: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested.. table 10. programming mode ac characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) programming the M27V401 has been designed to be fully com- patible with the m27c4001 and has the same electronic signature. as a result the M27V401 can be programmed as the m27c4001 on the same programming equipments applying 12.75v on v pp and 6.25v on v cc by the use of the same presto ii algorithm . when delivered (and after each erasure for uv eprom),all bits of the M27V401 are in the '1'state. data is introduced by selectively programming '0's into the desired bit locations. although only '0's will be programmed, both '1's and '0's can be present in the data word. the only way to change a '0' to a '1' is by die exposure to ultraviolet light (uv eprom). the M27V401 is in the programming mode when v pp input is at 12.75v, g at v ih and e is pulsed to v il . the data to be programmed is applied to 8 bits in parallel to the data output pins. the levels requiredfor the address and data inputs are ttl. v cc is specified to be 6.25v 0.25v. 7/15 M27V401
tavpl valid ai00725 a0-a18 q0-q7 v pp v cc g data in data out e tqvel tvphel tvchel tehqx teleh tglqv tqxgl tghqz tghax program verify figure 6. programming and verify modes ac waveforms presto ii programming algorithm presto ii programming algorithm allows the whole array to be programmed, with a guaranteed margin, in a typical time of 52.5 seconds. program- ming with presto ii involves in applying a se- quence of 100 m s program pulses to each byte until a correct verify occurs (see figure 7). during pro- gramming and verify operation, a margin mode circuit is automaticallyactivated in order to guaran- tee that each cell is programmed with enough margin. no overprogrampulse is applied since the verify in margin mode at v cc much higher than 3.6v provides necessary margin to each pro- grammed cell. program inhibit programming of multiple M27V401s in parallel with different data is also easily accomplished. except for e, all like inputs including g of the parallel M27V401 may be common. a ttl low level pulse applied to a M27V401's e input with v pp at 12.75v, will program that M27V401. a high level e input inhibits the other M27V401s from being pro- grammed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correctly programmed. the verify is accomplished with g at v il , e at v ih ,, v pp at 12.75v and v cc at 6.25v. ai00760b n=0 last addr verify e = 100 m s pulse ++n =25 ++ addr v cc = 6.25v, v pp = 12.75v fail check all bytes 1st: v cc =6v 2nd: v cc = 4.2v yes no yes no yes no figure 7. programming flowchart 8/15 M27V401
on-board programming the M27V401 can be directly programmed in the application circuit. see the relevant application note an620. electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its correspondingprogramming algorithm. the es mode is functional in the 25 c 5 c ambient temperature range that is required when program- ming the M27V401. to activate the es mode, the programming equipmentmust force 11.5vto 12.5v on address line a9 of the M27V401,with v pp =v cc = 5v. two identifier bytes may then be sequenced from the device outputs by togglingaddress line a0 from v il to v ih . all other address lines must be held at v il during electronic signature mode. byte 0 (a0=v il ) represents the manufacturer code and byte 1 (a0=v ih ) the device identifier code. for the stmicroelectronics M27V401, these two iden- tifier bytes are given in table 4 and can be read-out on outputs q0 to q7. note that the M27V401 and m27c4001 have the same identifier bytes . erasure operation (applies to uv eprom) theerasure characteristicsof the M27V401is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000?range. researchshows that constant exposure to room level fluorescent lighting could erase a typical M27V401 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the M27V401 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27V401 window to prevent unintentional erasure. the recommended erasure procedure for the M27V401 is exposure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the erasure time with this dosage is approximately 15 to 20 minutes using an ultra- violet lamp with 12000 m w/cm 2 power rating. the M27V401 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be re- moved before erasure. 9/15 M27V401
ordering information scheme speed -120 120ns -150 150ns -180 180ns -200 200ns package f fdip32w b pdip32 k plcc32 n tsop32 8 x 20mm temperature range 1 0 to 70 c 6 40 to 85 c option tr tape & reel packing example: M27V401 -120 k 6 tr for a list of available options (speed, package,etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 10/15 M27V401
drawing is not to scale. fdip32w - 32 pin ceramic frit-seal dip, with window fdipw-a a3 a1 a l b1 b e d s e1 e n 1 c a ea d2 ? eb a2 symb mm inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 .0177 b 0.41 0.56 0.016 0.022 b1 1.45 0.057 c 0.23 0.30 0.009 0.012 d 41.73 42.04 1.643 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.06 13.36 0.514 0.526 e 2.54 0.100 ea 14.99 0.590 eb 16.18 18.03 0.637 0.710 l 3.18 0.125 s 1.52 2.49 0.060 0.098 ? 7.11 0.280 a 4 11 4 11 n32 32 11/15 M27V401
pdip32 - 32 lead plastic dip, 600 mils width pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 symb mm inches typ min max typ min max a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 15.24 0.600 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 a 0 10 0 10 n32 32 drawing is not to scale. 12/15 M27V401
drawing is not to scale. plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 plcc32 - 32 lead plastic leaded chip carrier, rectangular 13/15 M27V401
tsop32 - 32 lead plastic thin small outline, 8 x 20mm tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.17 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 0.020 l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004 drawing is not to scale. 14/15 M27V401
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics. ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 15/15 M27V401

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